8-bit CPU from scratch
Designed the control unit, ALU, program-memory and data-memory access units in Verilog and ABEL. FSM control handles CALL/RTS subroutines and branching with synchronized memory reads and writes.
I build ML models and the hardware they run on, for problems with noisy data and real constraints.
Small live versions of things I have worked on. Every demo runs on synthetic data in your browser.
A 12-bit LFSR drives a band-limited channel. Add noise and jitter and watch the eye close.
Designed the control unit, ALU, program-memory and data-memory access units in Verilog and ABEL. FSM control handles CALL/RTS subroutines and branching with synchronized memory reads and writes.
Custom Transformer encoder on OHLCV plus engineered features (RSI, Bollinger Bands, MA slope) forecasting next-step returns, mapped to long/short positions and evaluated out-of-sample on Sharpe, P&L and max drawdown.
Bare-metal AVR assembly on an ATmega64: SPI driver for a 16-bit serial EEPROM, multiplexed 7-segment score display, debounced sensor matrix and timer-interrupt multi-tone audio.
PRBS transmitter on an FPGA over an ultra-wideband link, with a demodulator/decoder receiver chain.
Spare-parts demand across 50+ countries: classical baselines to a Temporal Fusion Transformer with calibrated intervals.
Beam profiling and cavity characterization; measured Q within 5% of theory.

I study Electrical Engineering (Intelligent Systems) at Caltech, class of 2027.
In industry I have built LLM and forecasting pipelines and done quantitative research. In research labs I have worked on FPGA, RF and optics hardware. I like problems where the answer is a measured number: an R², a signal fidelity, a cavity’s Q.
Before all that I built model airplanes and won Science Olympiad Nationals in Flight. I still think about lift and drag more than I should.
Pitch equities weekly to the investment committee and help rebalance a $1.4M portfolio.